1. Field of Invention
The present invention is related to a comparative latch, specifically, to a high-speed and low-offset dynamic comparative latch with less likely occurrence of mistuning.
2. Description of Related Arts
The high-speed dynamic comparative latch has the characteristics of high speed, low power consumption, high input impedance and full-swing output, and thus is applied widespreadly to the high-speed analog-to-digital converters, sense amplifiers and data receivers. The comparative latch is consisting of three parts, as shown in FIG. 1. One is the pre-amplifier unit, which enlarges the differential mode of input signals and outputs to the next part, regenerative latch; the second is the regenerative latch unit connected with the pre-amplifier unit, which uses a positive feedback to latch the differential mode signals; then the final part, a DFF unit (digital flip-flop) connected with the regenerative latch unit, which converts the latched differential mode signals to full-swing and outputs them out.
FIG. 2 is a circuit diagram of the current high-speed dynamic comparative latch.
Referring to FIG. 2, INP/INN is a pair of differential input signals; CLKP/CLKN is a pair of differential input clocks; OUT is the output of the high speed dynamic comparative latch.
The pre-amplifier unit A is consisting of a pair of input FET (Field Effect Transistor) M1 and M2, a pair of clock-controlled reset FET M4 and M5, and a clock-controlled FET transistor M3.
The regenerating latch unit is consisting of a pair of input-controlled FET M7 and M8, latching FET M11/M12/M13/M14, and a clock-controlled FET M0.
The DFF unit is consisting of two latches. One DFF unit is a high level latch unit that is consisting of a switch FET (Filed Effect Transistor) M6 controlled by the input clock CLKP, an inverter consisting of FET M18 and M19, and the other inverter consisting of FET M20 and M19, wherein the switch FET and the two inverters are connected with each other end to end; the other DFF unit is a low level latch unit that is consisting of a switch FET M21 controlled by clock CLKN, an inverter consisting of FET M10 and M16, and the other inverter consisting of FET M9 and M15, wherein they are connected with each other end to end.
When the clock CLKP changes from a low level to a high level, the clock CLKN changes from a high level to a low level, namely, CLKP is rising and CLKN is falling, the high-speed comparator changes from a reset mode to a working mode. The pair of reset FET M5/M4 of the pre-amplifier controlled by CLKP is turned off; the clock CLKP controls M3 to be turned on. The clock-controlled FET M0 of the regenerating latch controlled by the clock CLKN is turned on; the regenerating latch gets into a positive feedback latching mode form a reset mode. The nodes PB1/NB1 still stay in a low state (PB1=0/NB1=0). M6 of the DFF controlled by the clock CLKP is turned on, so the high-level latch gets into a latching state; M21 controlled by the clock CLKN is turned off, so the low-level latch gets into a holding state, and then the output OUT keeps the same.
When the clock CLKP is in a high level, the high speed comparator is in the latching mode. The differential mode of the input differential signals, after being enlarged by the pre-amplifier through node PA1, controls FET M7 of the regenerating latch and controls transistor M8 through node NA1; the regenerating latch reestablishes signals through M7 and M8, which inject currents proportionate to the differential mode of the input signals, and finally latches the inputted differential mode to a corresponding status. Once the reestablishment is done, even if the differential signals INP/INN change, the output of the regenerating latch will not change along with it. The clock CLKP controls the FET M6 of the latch to be turned on; that way, the high level latch gets into the latching status, and NC1 is latched as the output of the current regenerating latch; The clock CLKN controls M21 to be turned off, and the low level regenerating latch gets into a retaining status and the output OUT will keep the immediate previous status.
When the clock CLKP changes from the high level to the low level, and retains the low level, the high-speed comparator changes its working mode to a reset mode. In the pre-amplifier, the pair of reset FET M4/M5 is turned on and the FET M3 is turned off through the control of the clock CLKP; thus, the output of PA1/NA1 is pulled up to the power supply (PA1=1/NA1=1). In the regenerating latch, the clock CLKN controls the FET M0 to be turned off. Because PA1 and NA1 are pulled up to the power supply, the FET M7 is turned on through the control of PA1, and the node NB1 is pulled down to the ground; the FET M8 is turned on through the control of NA1, then the node PB1 is pulled down to the ground. In the latch, the FET M6 is turned off by the clock CLKP, so the high level latch gets into a retaining status, and NC1 is kept as the output of the immediate previous working mode of the regenerating latch. The clock CLKN controls M21 to be turned on, so the low level latch gets into the latching status, and so the output OUT is that one of the immediate previous working mode of the regenerating latch.
The existing high-speed dynamic comparative latch has the following shortcomings:                1) The circuit characteristics of the regenerating latch unit B make it necessary to use a pair of differential clocks, and the timing sequence of the two differential clocks need to match precisely with each other. As the clock rate of high speed systems is increasing, the requirement of precise matching of the differential clocks challenges the design and the implementation of the physical layer;        2) The circuit characteristics of the regenerating latch unit B determine that during the high level of a clock cycle it is in a working status, and during the low level it is in a reset status; namely, the output of the regenerating latch unit B is effective only during the period of the high level of the clock cycle, and the output during the period of the low level of the clock cycle is ineffective;        3) The regenerating latch circuit B needs a certain time to achieve latching, when it switches from a resetting status to a latching and outputting status; but the time depends on the transistors and parasitic parameters of the circuit; therefore it gets rise to an uncertain delay time of the output of the regenerating latch unit B under different technology and temperatures, relative to the rising edge of the clock, and accordingly compresses the effective values of the latch; if applied to take samples of a high speed clock, it will cause the erroneous output of the latch.        